I design hardware
and write software.
I'm a Computer Engineering student at Georgia Tech. I've worked on FPGA encryption, firmware for a sensory-feedback insole, and billing recovery tools at AWS.
- School
- Georgia Tech, BS Computer Engineering
- GPA
- 3.92
- Seeking
- Summer 2027 internship
- Based in
- Atlanta, GA
Explore my work by role
Choose a role to see a demo or results and bring related experience and projects to the top.
Experience
-
Amazon Web Services (AWS)
Software Development Engineer Intern
Route 53 billingAug 2026 to Dec 2026Tools to detect and recover failed billing daysDaily metering for ~73M health checks across 140K+ accounts- Route 53's daily billing job meters ~73M health checks across 140K+ accounts. Missed or incomplete runs leave billing gaps that can go unnoticed until month-end. Recovery previously required an eight-step, roughly seven-hour procedure with two operators.
- Built status and progress APIs so operators can see a day's outcome, per-host progress, and failure reasons. Status is reconciled against the PostgreSQL metering database.
- Built metrics and alarms that distinguish a failed job from an unknown result or a stalled monitoring process. Failures automatically create an incident ticket.
- The AI triage agent uses run context and logs to suggest fixes. It identified the correct fix for all 5 failed runs evaluated from September to October 2026.
- Built a Python Model Context Protocol (MCP) server, used by the on-call team, that lets the agent fetch billing-run context, search logs, and compare runs itself. Starting a recovery requires a named human approver.
- Built an on-demand recovery command with a second-reviewer approval step. It selects a host, runs alongside the current day's job, and stops if billing data or batch boundaries change to guard against duplicate charges. Operators can track the result and open logs for the affected day.
ToolsJava, Python, MCP SDK, Coral (service framework), Mechanic (operator CLI), PostgreSQL, DynamoDB, S3, CloudWatch Logs Insights, Carnaval alarms, pMET metrics
-
Greenlight Financial Technology
Data Engineering Intern
Data engineeringJun 2026 to Aug 2026Automated outage diagnosis and partner reporting~99% correct diagnosis; reporting cut from 2 to 3 days to 22 minutes- Built a read-only incident-response agent that traces data pipeline failures across job logs, warehouse queries, and code changes, then sends its diagnosis to Slack. Root causes were hand-graded: about 99% were correct across ~300 historical incidents and ~50 live incidents combined.
- Automated monthly reports for 12 partners, replacing 2 to 3 days of manual work with a 22-minute pipeline. It extracts and cleans data, checks it, writes a narrative, and delivers PDF and Excel reports. Fee reconciliation errors fell from about 8% to zero in the first 3 monthly runs.
- Fixed memory failures when 12 pipeline tasks converged. Changed Airflow tasks to release their worker slots while Databricks jobs ran, reducing worker slot time by 97%.
- Built an internal finance application in React and Python on Databricks, with projected licensing savings of $70,000 per year.
- Moved the support bot's knowledge base from Google Drive to an S3 ingestion pipeline, removing recurring OAuth refreshes. Indexed 1,400 documents for retrieval and reranking. Managed AWS, Snowflake, and Databricks infrastructure in Terraform.
- Separated production and staging permissions so staging jobs could no longer write to production. Added Snowflake masking policies to hide personal information in calendar event descriptions.
ToolsPython, Airflow, Snowflake, Databricks, PySpark, LangGraph, Pinecone, Terraform, AWS
-
CRNCH, Georgia Tech
Undergraduate Researcher, RTL Design and Verification
Open-source encryption hardwareJan 2026 to presentFaster encryption with four parallel FPGA coresCo-designed the hardware and led checks of timing and control behavior- Contributed to tiny-xcc, an open-source XChaCha20 and ChaCha20 encryption accelerator, as part of a 16-person team at Georgia Tech.
- Co-designed the four-core version with a teammate for the Ultra96-V2 FPGA board. Each core produces a 64-byte block in 21 clock cycles. Together they reach a compute peak of ~9.75 Gbps at 100 MHz without dedicated memory or DSP blocks.
- Led formal verification and co-wrote the verification plan. Wrote SystemVerilog assertions for the block core with a teammate, and for the add-rotate-xor cell and top-level controller. Bounded checks in SymbiYosys cover latency, request handling, and output stability: 25 cycles for the block core and up to 50 for the single-core top level.
- Profiled the board's 1.5 GHz Cortex-A53 software baseline at 11 to 16 cycles per byte. The four-core compute peak is about 9 to 13 times faster; host transfer overhead is excluded.
- Co-wrote the datasheet, design documentation, and integration guide so others can use the accelerator.
ToolsVerilog, SystemVerilog, SVA, SymbiYosys, Icarus Verilog, AXI4-Lite
Read the case study -
GT Student Government Association
Software Engineering Intern
Student funding reviewAug 2025 to presentPaused Fall 2026Cut funding review time from 25 to 5 minutesAI pre-review for 800+ annual requests across $10M in student funding- Shipped a Django platform that checks funding requests against university guidelines before committee review. The AI's initial check takes about 10 seconds; reviewers spend about 5 minutes checking its output, down from about 25 minutes manually. Across 800+ annual requests totaling $10M, that is roughly 260 reviewer-hours saved per year.
- Kept guideline documents whole so the model could read rules alongside nested exceptions. Compared answer quality across GPT-4o mini, Claude Haiku, and Gemini Flash. Haiku and Flash gave similar results; I chose Gemini 2.5 Flash for context capacity and batch cost.
- Trained an Isolation Forest without labels, then validated it against requests hand-labeled in past years. Precision was 94%. When raw request size dominated the results, I reworked the features to include organization spending history and cost per attendee.
- An extension to combine the guideline check and anomaly score into one report for reviewers is in progress.
- Presented the design to university administrators and faculty and secured approval for the production rollout.
ToolsPython, Django, Gemini 2.5 Flash, Google Cloud Vertex AI, scikit-learn, LangChain
-
SiliconJackets
Digital Design Member
Pipelined RISC-V processorAug 2025 to presentKeep a processor running while memory writes waitDesigning a write buffer for a student RISC-V chip with one teammate- Designing a Verilog write buffer with one teammate for a pipelined RISC-V processor intended for chip fabrication.
- The buffer queues pending stores and writes them to memory, allowing the processor to continue while buffer space is available.
ToolsVerilog, RISC-V
-
TerraSense
Co-founder and Lead Embedded Systems Engineer
Wearable startup, Create-XMay 2025 to presentTurn foot pressure into sensory feedbackCo-founded an insole startup; firmware responds in 2.36 ms on hardware- Co-founded TerraSense to build an insole that converts foot pressure into sensory feedback for people with amputation or diabetic neuropathy. The prototype combines pressure sensors, an ESP32-C6, and a custom electrical-stimulation circuit, with a price target under $100 compared with $900+ systems.
- Wrote C++ firmware that samples pressure at 200 Hz and uses an int8 neural network to classify stance in about 2.2 ms. Hardware timers and DMA move samples into alternating buffers; Bluetooth telemetry and output work stay separate from the sensing path.
- Measured 2.36 ms from sensing to feedback output, within our 5 ms target. Verified the timing with both hardware timers and GPIO traces on a logic analyzer.
- Changed direction from a prosthetic ankle to an insole after user interviews pointed to lost ground feedback as the problem to address.
- Accepted into Georgia Tech Create-X Startup Launch and demonstrated the prototype at Demo Day in Summer 2025.
ToolsC++, ESP32-C6, ESP-IDF, DMA, MCPWM, BLE, logic analyzer
Read the case study -
GT Experimental Rocketry
Avionics Firmware Engineer
Avionics teamGeorgia TechMake rocket flight sequences explicit and testableMapped six flight phases and separated control logic from hardware access- Audited the STM32 flight manager in bare-metal C, tracing how flight sequencing interacts with telemetry, GPS, state estimation, and recovery deployment.
- Documented six flight phases (pad safe, armed, boost, coast, descent, landed) and the sensor conditions that trigger each transition. Identified missing transition tests for the team.
- Separated hardware access into drivers so flight sequencing no longer reads or writes registers directly, removing a class of races with telemetry interrupts.
ToolsEmbedded C, STM32, bare metal
-
Georgia Tech VIP, IoT in Healthcare
Undergraduate Research Assistant
IoT in HealthcareAug 2025 to Dec 2025Designed a prosthetic foot to adapt to terrainSystem proposal targeting under $500 in parts- Proposed a prosthetic foot that uses motion sensors to detect terrain and gait, then adjusts through Nitinol actuators. Defined the sensing and actuation architecture around a 6-axis inertial sensor.
- Targeted a parts budget under $500 to address the cost of commercial feet, which can cost 40 to 140 times more. This work was a system proposal.
ToolsIMU, embedded systems design
-
Assets Edge
Software Engineering Intern
Retail software2023 to 2024Built a storefront with lower database latency15% higher conversion; 40% lower database query latency- Built a React and Node.js storefront for a $64M product catalog. User conversion increased by 15%.
- Profiled slow product queries and redesigned the MongoDB schema with compound indexes, cutting retrieval latency by 40%.
ToolsReact, Node.js, MongoDB
Projects
-
SCOMP processor extension
16-bit processor on an FPGA
CourseworkSpring 2025Built new CPU instructions in hardwareEight added instructions, plus hardware multiply, divide, and error flags- Extended a 16-bit teaching processor in VHDL on an Intel Cyclone V FPGA. Added subtraction, immediate addition, modulus, bitwise logic, and shifts: 8 new instructions in total.
- Built an arithmetic coprocessor for multiplication, division, and modulus. Added status registers so software can detect overflow and division by zero.
ToolsVHDL, Quartus Prime, Intel Cyclone V, assembly
NoteCode withheld under Georgia Tech academic policy.
-
Dual-train collision avoidance
Digital control for a model railway
CourseworkGeorgia TechCoordinate two trains to prevent collisionsTrack sensors drive motor direction and fail-safe switching- Designed a nine-state controller in VHDL that reads six asynchronous track sensors to coordinate two model trains.
- Implemented motor control in both directions and fail-safe track switching for worst-case sensor inputs.
ToolsVHDL, Quartus Prime
NoteCode withheld under Georgia Tech academic policy.
-
Linux TCP/UDP benchmark
Network performance measurement
Personal projectSummer 2026Measure how network settings affect speed and loss1,000+ automated trials across message sizes and socket configurations- Built a C++ benchmark to measure TCP and UDP latency, throughput, and packet loss on Linux, with message sizes from 64 bytes to 1 MB.
- Automated 1,000+ trials across socket buffer sizes, transfer patterns, and message counts to investigate how each setting affects network performance.
ToolsC++, Linux, TCP/IP, UDP, Bash, Python
-
OmniController
Accessible game controller
Hackathon buildSpring 2026Play games through motion and voiceTested in three games with no dropped inputs during the demo- Built ESP32 firmware that turns body motion into game input. Combined gyroscope and accelerometer readings from an MPU-6050 to estimate orientation, with calibration, deadzones, and flick detection to control unintended inputs.
- Mapped motion to a virtual Xbox controller through a Python host. Added speech-to-text commands for menus using ElevenLabs.
- Prioritized the core motion controls for the hackathon demo. They ran in all three test games with no dropped inputs.
ToolsESP32, C++, MPU-6050, Python, ElevenLabs STT
LinkDevpost
-
Embedded snake game
Hand-wired breadboard console
CourseworkGeorgia TechBuilt Snake on a hand-wired microcontroller consoleGame logic, button interrupts, and an external display- Wrote the game logic and a deterministic rendering loop in C on an mbed microcontroller.
- Hand-wired the breadboard console with an external LCD and interrupt-driven buttons for navigation.
ToolsC, mbed, GPIO, SPI, I2C
-
Memos
Personal notes and media tracker
Personal projectSpring 2026Keep notes on books, films, and games in one placeLower metadata latency; preserves conflicting offline edits- Built a notes app for tracking films, games, and books. A shared cache checks memory, then Firestore, before calling external metadata APIs; it also caches missing results. Time to first byte fell from 1 second to 700 ms.
- Moved IGDB API credentials into a Cloudflare Worker so they stay off the client. External API latency fell by 40% across the app's four APIs.
- Stored notes as Markdown and kept ratings, progress, and ordering in separate Firestore collections. Parsers turn Markdown sections into media galleries.
- Added client-side diffing to preserve conflicting offline edits rather than silently overwrite them.
ToolsReact, Firebase, Cloudflare Workers
LinkOpen the app
-
Re.Mind
Android app
Hackathon buildFall 2025Help people with dementia recognize familiar facesOffline prototype; 98% recognition accuracy on a 100+ case test set- Built an Android prototype that recognizes faces as a memory aid for people with dementia. Recognition runs entirely on the phone using ML Kit and TensorFlow Lite, with 98% accuracy on a 100+ case test set.
- Kept personal data on the device and tuned the camera lifecycle and memory use to avoid out-of-memory failures on low-end phones.
-
HistoreX
Textbook-to-storyboard app
Hackathon build2024Turn textbook passages into illustrated storyboardsGenerates a script and scene images in a working web app- Built a Streamlit app that turns textbook passages into storyboards. Gemini generates the script and Imagen 3 creates scene images; the app assembles them and handles API rate limits and errors.
ToolsPython, Streamlit, Gemini API, Imagen 3
LinksOpen the app · GitHub
Skills
Digital hardware
Verilog, SystemVerilog, VHDL, RTL, state machines, AXI4-Lite, memory-mapped I/O, AMD Zynq, Intel Cyclone V
Hardware verification
SystemVerilog assertions, SymbiYosys, bounded model checking, Icarus Verilog, Cadence Xcelium, Quartus Prime
Embedded firmware
ESP32-C6, ESP32, STM32, ESP-IDF, DMA, MCPWM, I2C, SPI, UART, Bluetooth LE, logic analyzer
Languages
C, C++, Python, Java, SQL, Bash, JavaScript, Kotlin, assembly (SCOMP)
Systems and data
Linux, AWS (DynamoDB, S3, Lambda), PostgreSQL, Airflow, Snowflake, Databricks, PySpark, Terraform, Docker
Applications and machine learning
React, Django, LangGraph, LangChain, retrieval-augmented generation, Pinecone, scikit-learn, TensorFlow Lite, int8 quantization, Git
About
I like problems where hardware and software have to agree. In an insole, that means feedback arrives within the sensing deadline. In an encryption core, it means the hardware produces the right result and tells software when it is ready.
TerraSense also taught me to question the starting idea. We began with a prosthetic ankle, but user interviews pointed us toward lost ground feedback. We redesigned it as an insole.
Georgia Institute of Technology
BS Computer Engineering · GPA 3.92
Relevant coursework: VLSI and advanced digital design, computer architecture, systems and concurrency, algorithms, hardware/software systems, and digital design lab.
Contact
Open to Summer 2027 internships.