Aarush Assudani
Computer Engineering Student
Computer Engineering Student
I'm a Computer Engineering student at Georgia Tech specializing in digital design and hardware architecture. I work with Verilog and VHDL to build systems that matter—from cryptographic accelerators on AMD Xilinx FPGAs to custom RISC processors. Currently, I'm developing a hardware-accelerated XChaCha20 encryption module and contributing to SiliconJackets' SoC tapeout initiative.
Expected Graduation: May 2027
Relevant Coursework: Physical Foundations of Computer Engineering (ECE 3030), Architecture, Systems, Concurrency & Energy (ECE 3058), VLSI and Advanced Digital Design (ECE 3150), Circuit Analysis (ECE 2040), Digital Design Laboratory (ECE 2031)
January 2025 - Present
2025 - Present
2024 - 2025
2023 - 2024
2023 - 2024
Multidisciplinary project developing hardware-accelerated stream cipher for encryption on AMD Xilinx Zynq UltraScale+ MPSoC. Designed modular RTL architecture implementing ARX (Add-Rotate-XOR) primitives, quarter round logic, and HChaCha subkey derivation with 256-bit key and 192-bit nonce support via MMIO and AXI4-Lite bus interfaces.
IoT-powered sensory prosthetic providing tactile feedback without invasive surgery, enhancing user mobility and quality of life. Developed through Georgia Tech's Create-X Launch accelerator program.
Developed AI-powered memory support application for dementia patients integrating Google ML Kit and TensorFlow Lite for facial recognition (98% accuracy), implementing dynamic cognitive prompt system that improved patient recall efficiency by 60% while engineering secure offline-first architecture ensuring complete patient data privacy
Developed a Snake game in C for a hardware/software class, implementing it on an mbed microcontroller. The game runs on a custom-built breadboard circuit featuring an LCD screen for display, a navigation switch for movement controls, and additional buttons for game functionality.
Developed AI-powered educational video generation platform integrating Google Gemini API for automated script creation from textbooks and Imagen3 API for visual asset generation, deploying interactive Streamlit web interface enabling users to input topics and generate custom educational video content
Student-led semiconductor project implementing multi-cycle addition system with split memory banks for 64-bit word processing as part of SoC tapeout initiative. Architected 64-bit addition using dual 32-bit ripple-carry adders with sequential carry propagation requiring 6 clock cycles per operation.
Designed 16-bit RISC processor in VHDL with full fetch-decode-execute pipeline, extending ISA from 15 to 20 instructions. Integrated memory-mapped I/O interface with 11-bit address bus and engineered custom arithmetic coprocessor peripheral with hardware-accelerated multiplication, division, and modulus operations.
Safety-critical 9-state Moore FSM for autonomous train control system with real-time collision avoidance logic processing 6 sensor inputs. Built bidirectional motor control logic with state-based track switch control ensuring fail-safe operation under all sensor conditions.
Feel free to reach out for collaboration opportunities, research inquiries, or just to say hello!