RTL Design · Embedded Systems · Firmware · Software
Building at the intersection of hardware and code — Georgia Tech ECE, 3.91
I design hardware and write the software that runs on it. From cryptographic accelerators on FPGAs to multi-threaded firmware on microcontrollers to full-stack web platforms — I work across the full stack of abstraction. Currently focused on RTL design & verification and embedded firmware for systems and medical applications.
I'm a Computer Engineering student at Georgia Tech specializing in digital design and hardware architecture. I work with Verilog and VHDL to build systems that matter: from cryptographic accelerators on AMD Xilinx FPGAs to custom RISC processors. Currently, I'm developing a hardware-accelerated XChaCha20 encryption module and contributing to SiliconJackets' SoC tapeout initiative.
Expected Graduation: May 2027
Relevant Coursework: Physical Foundations of Computer Engineering (ECE 3030), Architecture, Systems, Concurrency & Energy (ECE 3058), VLSI and Advanced Digital Design (ECE 3150), Circuit Analysis (ECE 2040), Digital Design Laboratory (ECE 2031)
Hardware-accelerated stream cipher on AMD Xilinx Zynq UltraScale+ MPSoC. 4 parallel ARX quarter-round cells with HChaCha20 subkey derivation. Hits 2.33 Gbps at 100 MHz in 22 cycles per 64-byte block using 4-7% LUT, no BRAM or DSP. Formally verified with 50+ SVA assertions across 10 modules.
IoT-powered sensory prosthetic providing tactile feedback without invasive surgery, enhancing user mobility and quality of life. Developed through Georgia Tech's Create-X Launch accelerator program.
Built with a 3-person team at a hackathon. A body-mounted controller that straps to any limb, letting people with limited or no hand motor control play any game. Wrote ESP32 firmware for the MPU-6050 IMU with on-the-fly switching between analog and discrete control modes. ElevenLabs STT handles launching games, remapping controls, and adjusting settings entirely via voice — no physical UI. Tested on Elden Ring, Forza, and Hades.
Notes and media watchlist app with Firestore backend, deployed via GitHub Actions CI/CD to GitHub Pages. Cloudflare Worker proxy for IGDB API access keeps secrets server-side. Firestore-backed cache layer across 4 media APIs (TMDB, IGDB, OpenLibrary, YouTube) eliminates redundant network calls.
Extended a 15-instruction RISC ISA to 20 instructions (SUB, JPOS, JNZ) in VHDL on Intel Cyclone V FPGA. Full fetch-decode-execute pipeline with MMIO across an 11-bit address bus. Custom arithmetic coprocessor with hardware multiply, divide, and modulus, plus dedicated registers for overflow and divide-by-zero detection.
Architected dual 32-bit ripple-carry adder with split SRAM banks for SiliconJackets SoC tapeout, enabling 64-bit addition in 6 clock cycles. Verified with Cadence Xcelium testbenches as part of the full physical design flow.
Safety-critical 9-state Moore FSM for autonomous train control system with real-time collision avoidance logic processing 6 sensor inputs. Built bidirectional motor control logic with state-based track switch control ensuring fail-safe operation under all sensor conditions.
Offline Android app for dementia patients. Facial recognition runs fully on-device via Google ML Kit and TensorFlow Lite — 98% accuracy across 100+ test cases, zero cloud dependency. Cognitive prompting system grounded in established memory support techniques gives patients personalized recall cues without sensitive data leaving the device.
Developed AI-powered educational video generation platform integrating Google Gemini API for automated script creation from textbooks and Imagen3 API for visual asset generation, deploying interactive Streamlit web interface enabling users to input topics and generate custom educational video content
Developed a Snake game in C for a hardware/software class, implementing it on an mbed microcontroller. The game runs on a custom-built breadboard circuit featuring an LCD screen for display, a navigation switch for movement controls, and additional buttons for game functionality.